Evaluating the SEE sensitivity of a 45nm SOI Multi-core Processor due to 14 MeV Neutrons

The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemented ECC and parity in their cache memories. Two different application scenarios are studied. The first one configures the multi-core in Asymmetric Multi-Processing mode running a memory-bound application, whereas the second one uses the Symmetric Multi-Processsing mode running a CPU-bound application. The experiments were validated through radiation ground testing performed with 14 MeV neutrons on the Freescale P2041 multi-core manufactured in 45nm SOI technology. A deep analysis of the observed errors in cache memories was carried-out in order to reveal vulnerabilities in the cache protection mechanisms. Critical zones like tag addresses were affected during the experiments. In addition, the results show that the sensitivity strongly depends on the application and the multi-processsing mode used

SEU Characterization of Three Successive Generations of COTS SRAMs at Ultralow Bias Voltage to 14.2 MeV Neutrons

This paper presents a SEU sensitivity characterization at ultra-low bias voltage of three generations of COTS SRAMs manufactured in 130 nm, 90 nm and 65 nm CMOS processes. For this purpose, radiation tests with 14.2 MeV neutrons were performed for SRAM power supplies ranging from 0.5 V to 3.15 V. The experimental results yielded clear evidences of the SEU sensitivity increase at very low bias voltages. These results have been cross-checked with predictions issued from the modeling tool MUlti-SCAles Single Event Phenomena Predictive Platform (MUSCA-SEP3). Large-scale SELs and SEFIs, observed in the 90-nm and 130-nm SRAMs respectively, are also presented and discussed

Statistical Deviations from the Theoretical only-SBU Model to Estimate MCU rates in SRAMs

This paper addresses a well-known problem that occurs when memories are exposed to radiation: the determination if a bitflip is isolated or if it belongs to a multiple event. As it is unusual to know the physical layout of the memory, this paper proposes to evaluate the statistical properties of the sets of corrupted addresses and to compare the results with a mathematical prediction model where all of the events are SBUs. A set of rules easy to implement in common programming languages can be iteratively applied if anomalies are observed, thus yielding a classification of errors quite closer to reality (more than 80% accuracy in our experiments)

Single Event Upsets under 14-MeV Neutrons in a 28-nm SRAM-based FPGA in Static Mode

A sensitivity characterization of a Xilinx Artix-7 FPGA against 14.2 MeV neutrons is presented. The content of the internal SRAMs and flip-flops were downloaded in a PC and compared with a golden version of it. Flipped cells were identified and classified as cells of the configuration RAM, BRAM, or flip-flops. SBUs and MCUs with multiplicities ranging from 2 to 8 were identified using a statistical method. Possible shapes of multiple events are also investigated, showing a trend to follow wordlines. Finally, MUSCA SEP3 was used to make assesment for actual environments and an improvement of SEU injection test is proposed

Vacuum System Models for Minerva Linac Design

International audienceThe goal of the MYRRHA project is to demonstrate the technical feasibility of transmutation in a 100 MW Accelerator Driven System (ADS) by building a new flexible irradiation complex at Mol (Belgium). The MYRRHA facility requires a 600 MeV accelerator delivering a maximum proton current of 4 mA in continuous wave operation, with an additional requirement for exceptional reliability. Supported by SCK•CEN and the Belgian federal government the project has entered in its phase I: this includes the development and the construction of the linac first part, up to 100 MeV. We here review the MINERVA linac vacuum system modelling studies that enabled to validate the choice of materials and vacuum equipment. The strengths and weaknesses of the vacuum design, highlighted by the models, will be discussed as well as the required improvements

Assessment of Current Sensor on Chip for Detecting Neutron-Induced Transients via Body Terminals

International audienceThis work assesses for the first time a body built-in current sensor in a CMOS 65-nm test chip under neutron radiation and laser irradiation. The sensor is effective to detect transient faults induced from both

Some Properties of only-SBUs Scenarios in SRAMs Applied to the Detection of MCUs

International audienceStatistical properties of experiments in SRAMs with only SBUs are mathematically evaluated. Strategies using deviations of actual data from theory are proposed to extract MCUs from the bulk of errors regardless the SRAM internal structure

Assessment of a Hardware-Implemented Machine Learning Technique under Neutron Irradiation

International audienceHardware-implemented intelligent systems running autonomous functions and decisions are today becoming more and more ubiquitous in many fields of applications, demanding reliable operation even under harsh conditions as in nuclear power plants and avionics altitudes. Support vector machine (SVM) is a prominent machine learning solution to optimize hardware-implemented autonomous systems. This paper is the first to assess the operation of a field-programmable gate array (FPGA)-designed SVM architecture under radiation effects. A fault emulation campaign along with radiation test experiments with a 14-MeV neutron generator has been performed, and the results show that 27% of the neutron radiation-induced errors in the target SVM architecture provoked critical failures